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T6020M
Low-Current Microcontroller for Watchdog Function
The T6020M is a member of TEMIC's family of 4-bit single-chip microcontrollers. It contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input, integrated RCoscillators.
Features / Benefits
D Programmable system-clock with prescaler and five different clock sources D Very low sleep current (< 1 A) D Very low power consumption in active, power-down and sleep mode D 2-Kbyte ROM, 256 x 4-bit RAM D 12 bidirectional I/Os D Up to 6 external / internal interrupt sources
V SS VDD
D Synchronous serial interface (2-wire, I2C, 3-wire) D Multifunction timer/counter with D Watchdog, POR and brown-out function D Voltage monitoring incl. Lo_BAT detect D Flash controller M48C893 available (SSO20) D Code-efficient instruction set D High-level language programming with qFORTH compiler
OSC1
Brown-out protect. RESET Voltage monitor External input VMI
RC oscillators
External clock input UTCM Timer 1 interval- and watchdog timer
Clock management
ROM
2 K x 8 bit
RAM
256 x 4 bit
BP20/NTE Data direction Port 2 BP21 BP22 BP23
MARC4
4-bit CPU core I/O bus
Data direction + interrupt control Port 5
Timer 2 8/12-bit timer with modulator SSI Serial interface
T2I T2O SD SC
Data direction + alternate function Port 4
BP42 BP40 INT3 T2O BP43 SC BP41 INT3 VMI SD T2I
BP50 BP52 INT6 INT1 BP53 BP51 INT1 INT6
Figure 1. Block diagram of the T6020M
Rev. A1, 03-Apr-00
1 (54)
Preliminary Information
AA A A AA AA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAA A AAAA A A A A A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A AAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A
Table 1. Pin description
T6020M
2 (54) BP50 BP51 BP52 BP53 n.c. n.c. n.c. OSC1 BP42 BP43 BP41 VDD VSS n.c. n.c. BP20 BP21 BP22 BP23 BP40 Name Type I/O I/O I/O I/O -- -- -- I I/O I/O I/O -- -- I/O I/O I/O I/O I/O Bidirectional I/O Bidirectional I/O Bidirectional I/O Bidirectional I/O Not connected Not connected Not connected Oscillator input Bidirectional I/O line of Port 4.2 Bidirectional I/O line of Port 4.3 Bidirectional I/O line of Port 4.1 Supply voltage Circuit ground Not connected Not connected Bidirectional I/O Bidirectional I/O Bidirectional I/O Bidirectional I/O Bidirectional I/O
BP40/INT3/SC 2
Function
BP50/INT6
BP51/INT6
BP52/INT1 4
BP53/INT1
Preliminary Information
line line line line line line line line line
OSC1 VDD n.c. 10 n.c. n.c.
of of of of
of of of of of
Figure 2. Pinning SSO20 package
Port Port Port Port
Port Port Port Port Port
6
5
8
7
3
1
9
5.0 5.1 5.2 5.3
2.0 2.1 2.2 2.3 4.0
T6020M
External clock input or external trimming resistor input
--- --- --- --- NTE-test mode enable --- --- --- SC-serial clock or INT3 external interrupt input VMI voltage monitor input or T2I external clock input Timer 2 T2O Timer 2 output SD serial data I/O or INT3-external interrupt input INT6 external interrupt input INT6 external interrupt input INT1 external interrupt input INT1 external interrupt input
Alternate Function
12
13
14
15
16
17
18
19
20
11
BP20/NTE
BP22
BP42/T2O
VSS
n.c.
n.c.
BP21
BP23
BP41/VMI/T2I
BP43/INT3/SD
Rev. A1, 03-Apr-00 Pin-No. SSO20 1 20 10 11 13 14 15 16 2 6 5 4 3 9 12 7 8 18 19 17 Input Input Input Input -- -- -- Input Input Input Input State NA NA -- -- Input Input Input Input Input Reset
T6020M
Table of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.7 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Power-on Reset and Brown-out Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 External Clock Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Voltage Monitor Control / Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Oscillator Circuits and External Clock Input Stage . . . . . . . . . . . . . . . . . . . . . . . . RC-Oscillator 1 Fully Integrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC-Oscillator 2 with External Trimming Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Management Register (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Bidirectional Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Data Register (P2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Control Register (P2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Bidirectional Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Bidirectional Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Universal Timer/Counter / Communication Module (UTCM) . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1 Control Register 1 (T1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1 Control Register 2 (T1C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Control Register (WDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 6 6 6 7 9 9 9 9 11 11 11 12 13 13 13 14 15 15 16 16 16 16 16 17 17 18 19 19 20 21 21 21 22 24 25 26 27 27 28
3
Rev. A1, 03-Apr-00
3 (54)
Preliminary Information
T6020M
Table of Contents (continued)
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Control Register (T2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Mode Register 1 (T2M1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Mode Register 2 (T2M2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Compare and Compare Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Compare Mode Register (T2CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 COmpare Register 1 (T2CO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 COmpare Register 2 (T2CO2) Byte Write . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Peripheral Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bit Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-bit Shift Mode (I2C compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bit Pseudo I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Control Register 1 (SIC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Control Register 2 (SIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Status and Control Register (SISC) . . . . . . . . . . . . . . . . . . . . . . . Serial Transmit Buffer (STB) - Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Receive Buffer (SRB) - Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Combination Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combination Mode Timer 2 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 28 29 30 31 34 34 35 36 37 37 37 37 38 38 38 39 40 41 41 42 42 44 44 44 45 45 46 46 46 49 49 49 51 52 53
4
5 6
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Rev. A1, 03-Apr-00
Preliminary Information
T6020M
1 Introduction
The T6020M is a member of TEMIC Semiconductors' family of 4-bit single-chip microcontrollers. They contain ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-oscillators. CPU is based on the HARVARD architecture with physically separate program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes both, an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density.
2
2.1
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripherals. The
Reset
Reset Clock
System clock
Sleep
Rev. A1, 03-Apr-00
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MARC4 CORE
PC X Y SP RP
Program memory
RAM
256 x 4-bit
Instruction bus
Instruction decoder Interrupt controller
Memory bus
TOS
CCR
ALU
I/O bus
On-chip peripheral modules
Figure 3. MARC4 core
94 8973
5 (54)
Preliminary Information
T6020M
2.2 Components of MARC4 Core
7FFFh 1F8 h 1F0h 1 E8h 1 E0h 1 E0 h 1 C0 h 18 0h INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
(2 K x 8 bit)
SCALL addresses
ROM
Z ero p age
14 0h 1 00 h 0 C0 h 0 80 h
1FFh
Zero page
000h
0 20 h 01 8 h 01 0 h 00 8h 0 00 h
04 0h
00 8h 0 00 h
$RESET $AUTOSLEEP
13391
Figure 4. ROM map of T6020M
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction decoder and interrupt controller. The following sections describe each functional block in more detail:
the return stack and data memory for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands from, and return their results to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth.
2.2.1
ROM
The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 2 Kbytes. An additional 1 Kbyte of ROM exists which is reserved for quality control self-test software The lowest user ROM address segment is taken up by a 512 byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in figure 4. Look-up tables of constants can also be held in ROM and are accessed via the MARC4's built-in TABLE instruction.
2.2.2
RAM
The T6020M contains 256 x 4-bit wide static random access memory (RAM). It is used for the expression stack,
6 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
FCh FFh Global variables
RAM address register:
X Y SP RP
04h 00h
Return stack Global v 07h variables 03h
Figure 5. RAM map
2.2.3
Registers
The MARC4 controller has seven programmable registers and one condition code register. They are shown in the following programming model. Program Counter (PC) The program counter (PC) is a 12-bit register which contains the address of the next instruction to be fetched
11
from the ROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. For linear code (no calls or branches) the program counter is incremented with every instruction cycle. If a branch-, call-, return-instruction or an interrupt is executed, the program counter is loaded with a new address. The program counter is also used with the TABLE instruction to fetch 8-bit wide ROM constants.
0
PC
7 0
RP
7
0
0
0
SP
7 0
X
7 0
Y
3 0
TOS
3 0
CCR
C
-- B
I
Figure 6. Programming model
Rev. A1, 03-Apr-00
Preliminary Information
IIIII IIIII
TOS-1
Expression stack
Return stack
11 0 RP
Program counter Return stack pointer Expression stack pointer
RAM address register (X) RAM address register (Y) Top of stack register Condition code register
Interrupt enable Branch Reserved Carry / borrow
III III
3 0 TOS TOS-1 TOS-2 4-bit 12-bit
(192 x 4-bit) Autosleep
RAM
Expression stack
SP
IIIII IIIII I IIIII I IIIIIII IIIIIII IIIII IIIIIII IIIIII IIII
IIIII IIIII
13392
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T6020M
RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer (SP) contains the address of the next-totop 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack pointer has to be initialized with " >SP S0 " to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically preincrements if an element is moved onto the stack, or it post-decrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized via ">RP FCh ". RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement addressing mode arrays in the RAM can be compared, filled or moved. Top Of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register (CCR) The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no affect on the C-flag. Branch (B) The branch flag controls the conditional program branching. Should the branch flag have been set by a previous instruction a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or on executing the DI instruction, the interrupt enable flag is reset thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI, RTI or SLEEP instruction.
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Rev. A1, 03-Apr-00
Preliminary Information
T6020M
2.2.4 ALU
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR).
2.2.5
I/O Bus
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section "Peripheral Modules". The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the MARC4 emulation (see also the section "Emulation").
2.2.6
Instruction Set
The MARC4 instruction set is optimized for the high level programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline allowing the controller to prefetch an instruction from ROM at the same time as the present instruction is being executed.
Rev. A1, 03-Apr-00
IIIII IIII IIIII III II II IIIIIIII IIII IIIIIIIII IIII I IIII II I III I IIIIIIIIIIIIII I III II I I IIIII IIIIIIIIIIII IIII IIII IIIIIIIIIIIIIIIIII II IIIIIIII IIIII IIII IIIII IIII
RAM SP TOS-1 TOS-2 TOS-3 TOS-4 TOS ALU CCR
Figure 7. ALU zero-address operations
94 8977
The MARC4 is a zero address machine, the instructions containing only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single machine cycle. For more information refer to the "MARC4 Programmer's Guide".
2.2.7
Interrupt Structure
The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the ROM (see table 2). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered, but the interrupt routine only started after the I flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module. (see section "Peripheral Modules").
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Preliminary Information
T6020M
INT7
7 6 Priority level 5 4 3 2 1 0
INT3
INT5
INT3 active
Main / Autosleep
Time
Figure 8. Interrupt handling
Interrupt Processing For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-bit wide "interrupt pending" and "interrupt active" registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register, it signals the CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the current PC is saved on the return stack. An interrupt service routine is completed with the RTI instruction. This instruction sets the interrupt enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt
service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). It should also be noted that automatic stacking of the RBR is not carried out by the hardware and so if ROM banking is used, the RBR must be stacked on the expression stack by the application program and restored before the RTI. After a master reset (power-on, brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are all reset. Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles depending on the state of the core).
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Preliminary Information
AAAA AAAA AAAA I AAAIIIIII IIIIIII A
AAAI IA AAAAAAAAI IIIIII AIIII AAAAAI
AAA AAAA AAA AAAA AAAA AAAA
INT7 active RTI INT5 active INT2
RTI
AAA AAA
RTI
INT2 pending
INT2 active
RTI
SWI0
INT0 pending
INT0 active
RTI
AAAAA AAAAA
Main / Autosleep
94 8978
Rev. A1, 03-Apr-00
T6020M
Table 2. Interrupt priority table
A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA A AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A A
INT2 INT3 INT4 INT5 INT6 INT7 | | 0C0h 100h 140h 180h 1C0h 1E0h D8h (SCALL 0C0h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) | | highest FCh (SCALL 1E0h)
Table 3. Hardware interrupts
Interrupt INT0 INT1
Priority lowest |
ROM Address 040h 080h
Interrupt Opcode C8h (SCALL 040h) D0h (SCALL 080h)
Function Software interrupt (SWI0) External hardware interrupt, any edge at BP52 or BP53 Timer 1 interrupt SSI interrupt or external hardware interrupt at BP40 or BP43 Timer 2 interrupt Software interrupt (SW15) External hardware interrupt, at any edge at BP50 or BP51 Voltage monitor (VM) interrupt
Interrupt INT1 INT2 INT3 INT4 INT6 INT7
AAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A
T1M SISC T2CM P5CR VCM Any edge at BP52 any edge at BP53 Timer 1 SSI buffer full / empty or BP40/BP43 interrupt Timer 2 compare match / overflow Any edge at BP50, any edge at BP51 External / internal voltage monitoring
Register P5CR
Interrupt Mask Bit P52M1, P52M2 P53M1, P53M2 T1IM SIM T2IM P50M1, P50M2 P51M1, P51M2 VIM
Interrupt Source
Software Interrupts
2.3
Master Reset
The programmer can generate interrupts by using the software interrupt instruction (SWI) which is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution.
Hardware Interrupts
In the T6020M, there are eleven hardware interrupt sources with seven different levels. Each source can be masked individually by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in table 4.
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an external input clock supervisor stage (see figure 9). A master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. During the power-on reset phase the I/O bus control signals are set to 'reset mode' thereby initializing all on-chip peripherals. All bidirectional ports are set to input mode. Attention: During any reset phase, the BP20/NTE input is driven towards VDD by a strong pull-up transistor. Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h. This activates the initialization routine $RESET which in turn has to initialize all necessary RAM variables, stack pointers and peripheral configuration registers (see table 7).
Rev. A1, 03-Apr-00
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Preliminary Information
T6020M
V DD Pull-up CL NRST res Reset timer Internal reset
CL=SYSCL/4 Power-on reset Brown-out detection Watch- dog res Ext. clock supervisor Figure 9. Reset configuration VDD VSS VDD VSS CWD
ExIn
13752
2.3.1
Power-on Reset and Brown-out Detection
The T6020M has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed . These circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been
V DD
reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power down mode is activated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down mode the brownout detection is disabled. Two values for the brown-out voltage threshold are programmable via the BOT-bit in the SC-register.
4.0 V 3.0 V
t d CPU Reset CPU Reset BOT = '1' td BOT = '0' td = 1.5 ms (typically) BOT = 1, low brown-out voltage threshold. (3.0 V) is reset value. BOT = 0, high brown-out voltage threshold (4.0 V). Figure 10. Brown-out detection td
t
14201
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Rev. A1, 03-Apr-00
Preliminary Information
T6020M
A power-on reset pulse is generated by a VDD rise across the default BOT voltage level (3.0 V). A brown-out reset pulse is generated when VDD falls below the brown-out voltage threshold. Two values for the brown-out voltage threshold are programmable via the BOT-bit in the SC-register. When the controller runs in the upper supply voltage range with a high system clock frequency, the high threshold must be used. When it runs with a lower system clock frequency, the low threshold and a wider supply voltage range may be chosen. For further details, see the electrical specification and the SC-register description for BOT programming.
2.4
Voltage Monitor
2.3.2
Watchdog Reset
The voltage monitor consists of a comparator with internal voltage reference. It is used to supervise the supply voltage or an external voltage at the VMI-pin. The comparator for the supply voltage has two internal programmable thresholds one lower threshold (4.0 V) and one higher threshold (5.0 V). For external voltages at the VMI-pin, the comparator threshold is set to VBG = 1.25 V. The VMS-bit indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS-bit is set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit (VIM) is reset in the VMC-register.
V DD
The watchdog's function can be enabled at the WDC-register and triggers a reset with every watchdog counter overflow. To supress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources.
Voltage monitor BP41/ VMI IN OUT INT7
2.3.3
External Clock Supervisor
VMC :
VM2 VM1 VM0 VIM
The external input clock supervisor function can be enabled if the external input clock is selected within the CM- and SC-registers of the clock module. The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources.
VMST :
-
-
res VMS
13754
Figure 11. Voltage monitor
Rev. A1, 03-Apr-00
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Preliminary Information
T6020M
2.4.1 Voltage Monitor Control / Status Register
Primary register address: 'F'hex Bit 3 VM2 --- Bit 2 VM1 --- Bit 1 VM0 Bit 0 VIM
AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA
AAAAAAAAAA A A AAAAAAAAAA A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAA AA
VMC: Write Reset value: 1111b VMST: Read reserved VMS Reset value: xx11b VM2: Voltage monitor Mode bit 2 VM1: Voltage monitor Mode bit 1 VM0: Voltage monitor Mode bit 0 VM2 1 1 1 1 0 0 0 0 VM1 1 1 0 0 1 1 0 0 VM0 1 0 1 0 1 0 1 0 Function Disable voltage monitor External (VIM-input), internal reference threshold (1.25 V), interrupt with negative slope Not allowed External (VMI-input), internal reference threshold (1.25 V), interrupt with positive slope Internal (supply voltage), high threshold (5.0 V), interrupt with negative slope Not allowed Internal (supply voltage), low threshold (4.0 V), interrupt with negative slope Not allowed VIM Voltage Interrupt Mask bit VIM = 0, voltage monitor interrupt is enabled VIM = 1, voltage monitor interrupt is disabled VMS Voltage Monitor Status bit VMS = 0, the voltage at the comparator input is below Vref VMS = 1, the voltage at the comparator input is above Vref
Low threshold VMS = 1 V DD High threshold 5.0 V 4.0 V Low threshold VMS = 0 High threshold
16530
Figure 12. Internal supply voltage supervisor Internal reference level VMI Negative slope VMS = 1 1.25 V VMS = 0 Positive slope Interrupt negative slope Figure 13. External input voltage supervisor t VMS = 0 Interrupt positive slope VMS = 1
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Rev. A1, 03-Apr-00
Preliminary Information
T6020M
2.5
2.5.1
Clock Generation
Clock Module
The T6020M contains a clock module with two different internal RC-oscillator types. OSC1 can be used as input for external clocks or to connect an external trimming resistor for the RC-oscillator 2. All necessary circuitry except the trimming resistor is integrated on-chip. One of these oscillator types or an external input clock can be selected to generate the system clock (SYSCL). In applications that do not require exact timing, it is possible to use the fully integrated RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency tolerance is better than 50%. The RC-oscillator 2 is a trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor attached between OSC1 and GND. In this configuration, the RC-oscillator 2 frequency can be maintained stable to within a tolerance of 15% over the full operating temperature and voltage range.
The clock module is programmable via software with the clock management register (CM) and the system configuration register (SC). The required oscillator configuration can be selected with the OS1-bit and the OS0-bit in the SC-register. A programmable 4-bit divider stage allows the adjustment of the system clock speed. A special feature of the clock management is that an external oscillator may be used and switched on and off via a port pin for the power-down mode. Before the external clock is switched off, the internal RC-oscillator 1 must be selected with the CCS-bit and then the SLEEP mode may be activated. In this state an interrupt can wake up the controller with the RC-oscillator, and the external oscillator can be activated and selected by software. A synchronization stage avoids too short clock periods if the clock source or the clock speed is changed. If an external input clock is selected, a supervisor circuit monitors the external input and generates a hardware reset if the external clock source fails or drops below 500 kHz for more than 1 msec.
OSC1 Oscin
RC oscillator 1 Ext. clock
ExIn ExOut Stop Stop RCOut1 Control IN1 Cin IN2 Divider /2 /2 /2 /2
SYSCL
RC oscillator2
RTrim RCOut2 Stop Sleep WDL CCS CSS1 CSS0 Cin/16
Osc-Stop
SUBCL
CM: NSTOP
SC:
BOT
---
OS1
OS0
Figure 14. Clock module Table 4. Clock modes
Mode 1 2 OS1 1 0
AAAAAAAAAA A A A AAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AA
Cin / 16 Cin / 16 Rev. A1, 03-Apr-00 15 (54)
Clock Source for SYSCL OS0 CCS = 1 CCS = 0 1 RC-oscillator 1 (intern) External input clock 1 RC-oscillator 1 (intern) RC-oscillator 2 with external trimming resistor
Clock Source for SUBCL
Preliminary Information
T6020M
The clock module generates two output clocks. One is the system clock (SYSCL) and the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCL can supply only the peripherals with clocks. The modes for clock sources are programmable with the OS1-bit and OS0-bit in the SCregister and the CCS-bit in the CM-register.
Ext. input clock Ext. OSC1 Clock ExOut ExIn Stop RcOut1 Osc-Stop CCS Clock monitor Res
2.5.2
Oscillator Circuits and External Clock Input Stage
Figure 16. External input clock
RC-Oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use the fully integrated RC oscillator 1. It operates without any external components and saves additional costs. The RC-oscillator 1 center frequency tolerance is better than 50% over the full temperature and voltage range. The basic center frequency of the RC-oscillator 1 is fO [4.0 MHz The RC oscillator 1 is selected by default after power-on reset.
RC oscillator 1 RcOut1 Stop RcOut1 Osc-Stop
Control
13758
Figure 15. RC-oscillator 1
External Input Clock
The OSC1 can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. Additionally the external clock stage contains a supervisory circuit for the input clock. The supervisor function is controlled via the OS1, OS0-bit in the SC-register and the CCS-bit in the CMregister. If the external input clock fails and CCS = 0 is set in the CM-register, the supervisory circuit generates a hardware reset. The input clock has failed if the frequency is less than 500 kHz for more than 1 ms.
16 (54)
Preliminary Information
AAAAAAAAAAAAAAA A AA AAAAAAAAAA AA A A AA AAAAAAAAAAAAAAA AAAAAA AA AAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAA AAAAAA AA
RC-Oscillator 2 with External Trimming Resistor
The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between OSC1 and VDD. In this configuration, the RC-oscillator 2 frequency can be maintained stable to within a tolerance of 10% over the full operating temperature and, voltage range from VDD = 3.5 V to 5.5 V. For example: An output frequency at the RC-oscillator 2 of 1.6 MHz, can be obtained by connecting a resistor Rext = 47 kW (see figure 17).
RC oscillator 2 OSC1 Rext RcOut2 RTrim Stop RcOut2 Osc-Stop
16532
The T6020M consists of two different internal RCoscillators and one external clock input stage.
OS1 1 1 x
OS0 1 1 0
CCS Supervisor Reset Output (Res) 0 enable 1 disable xAAAAAAAAAA disable
Figure 17. RC-oscillator 2
2.5.3
Clock Management
The clock management register controls the system clock divider and synchronization stage. Writing to this register triggers the synchronization cycle.
Rev. A1, 03-Apr-00
AAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops.
AAAAAA AAAAAA A A A A AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
Clock Management Register (CM)
CSS1 CSS0 CCS NSTOP CM: Not STOP peripheral clock NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode Core Clock Select CCS = 1, the internal RC-oscillator 1 generates SYSCL CCS = 0, an external clock source or the RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on the setting of OS0 and OS1 in the system configuration register Core Speed Select 1 Core Speed Select 0 CSS1 0 1 1 0 Bit 3 NSTOP Bit 2 CCS CSS0 0 1 0 1 Bit 1 CSS1 Divider 16 8 4 2 Bit 0 CSS0 Reset value Note Auxiliary register address: '3'hex Reset value: 1111b
Rev. A1, 03-Apr-00
System Configuration Register (SC)
OS1 OS0
BOT
SC: write
Mode 1 2
OS1 1 0
Brown-Out Threshold BOT = 1, low brown-out voltage threshold (3.0 V) BOT = 0, high brown-out voltage threshold (4.0 V) Oscillator Select 1 Oscillator Select 0
OS0 1 1
Bit 3 BOT
Preliminary Information
Bit 2 --- Input for SUBCL Cin / 16 Cin / 16 Bit 1 OS1 Bit 0 OS0 Selected Oscillators RC-oscillator 1 and external input clock RC-oscillator 1 and RC-oscillator 2 Primary register address: '3'hex Reset value: 1x11b
T6020M
17 (54)
T6020M
2.6 Power-down Modes
The sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications where the C is not fully utilized. In this mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruction. This instruction sets the interrupt enable bit (I) in the condition code register to enable all interrupts and stops the core. During the sleep mode the peripheral modules remain active and are able to generate interrupts. The C exits the sleep mode by carrying out any interrupt or a reset. The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. The total power consumption is directly proportional to the active time of the C. For a rough estimation of the expected average system current consumption, the following formula should be used: Itotal (VDD,fsyscl) = ISleep + (IDD IDD depends on VDD and fsyscl. The T6020M has various power-down modes. During the sleep mode the clock for the MARC4 core is stopped. With the NSTOP-bit in the clock management register (CM) it is programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped the selected oscillator is switched off. tactive / ttotal)
Table 5. Power-down modes
Mode Active Power-down SLEEP
CPU Core RUN SLEEP SLEEP
Osc-Stop* NO NO YES
AAAAAAA A AA A A A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A
* Osc-Stop = SLEEP & NSTOP & WDL 18 (54) Rev. A1, 03-Apr-00
Brown-out Function Active Active STOP
RC-Oscillator 1 RC-Oscillator 2 RUN RUN STOP
External Input Clock YES YES STOP
Preliminary Information
T6020M
3
3.1
Peripheral Modules
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O bus (see figure 21). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme has been adopted to enable direct addressing of the "primary register". To address the "auxiliary register", the access must be switched with an "auxiliary switching module". Thus a single IN (or OUT) to the module address will read (or write) into the module Module ASW Module M1
(Address Pointer) Subaddress Reg. Auxiliary Switch Module Bank of Primary Regs. Subport Fh 1 Subport Eh Subport 1 Subport 0 2
primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte wide registers are accessed by multiple IN- (or OUT-) instructions. For more complex peripheral modules, with a larger number of registers, extended addressing is used. In this case a bank of up to 16 subport registers are indirectly addressed with the subport address. The first OUT-instruction writes the subport address to the subaddress register, the second IN- or OUT-instruction reads data from or writes data to the addressed subport. Module M2
Aux. Reg.
Module M3
5
Primary Reg.
Primary Reg. Primary Reg. 3 4
6
I/O bus
to other modules
Indirect Subport Access (Subport Register Write)
3 1 2
Dual Register Access (Primary Register Write) OUT OUT 4 OUT IN (Primary Register Rea d) 3 Address(M 2) (Auxiliary Register Rea d)
4
Single Register Access (Prima ry Register Write)
6
Addr.(SPort) Addr.(M1) SPort_Data Addr.(M1) (Subport Register Read)
Prim._Data
Address(M2) OU T
Prim._Data Address(M3) O UT (Prima ry Register Read)
( Auxiliary Register Write ) Address(M2) Address(ASW) OUT Aux._Data Address(M2) OUT 5 6 Address(M3) IN
1 2
Addr.(SPort) Addr.(M1) Addr.(M 1)
Example of qFORTH Program Code
(Subport Register Write Byte) 1
2 2
IN
Addr.(SPort) Addr.(M1) SPort_Data(lo) Addr.(M1)
OUT OUT 5
SPort_Data(hi) Addr.(M1) OUT (Subport Register Rea d Byte)
Address(M2) Address(ASW) OUT Address(M 2) IN (Auxiliary Register Write Byte)
1 2 2
Addr.(SPort) Addr.(M1) Addr.(M 1) Addr.(M 1)
OUT IN (hi) IN (lo)
4 5 5
Address(M2) Address(ASW) OUT Aux._Data(lo) Address(M2) OUT Aux._Data(hi) Address(M2) OUT Aux._Data (hi) = da ta to be written into Auxiliar y Register (high nibble) SPort_Data(lo) = data to be written into SubP ort (low nibble) SPort_Data(hi) = da ta to be written into Subport (high nibble) (lo) = SPort_Data (low nibble) (hi) = SPort_Data (high nibble)
13357
Addr.(ASW) = Auxiliary Switch Module Address Addr.(Mx) = Module Mx Addr ess Addr.(SPort) = Subport Address Prim._Data = data to be written into Primar y Register. Aux._Data = da ta to be written into Auxilia ry Register Aux. _Data (lo ) = data to be written into Auxiliar y Re gister (low nibble )
Figure 18. Example of I/O addressing
Rev. A1, 03-Apr-00
19 (54)
Preliminary Information
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAA A A A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAA AAA A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AA AA AA AA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AA A AA A AA A AA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AA AA AA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AA A AAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA AA AA A AA A AA A AA A AAA A AA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA A A A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AA AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA AAAAAAAAAAA A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA A A A AA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AA AA AA AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAA AA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA
Table 6.Peripheral addresses
All ports (2, 4 and 5) are 4 bits wide. All ports may be used for data input or output. All ports are equipped with Schmitt trigger inputs and a variety of mask options for open drain, open source, full complementary outputs, pull up and pull down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address and the Port Control Register (PxCR), to the corresponding auxiliary register.
3.2
T6020M
20 (54)
B C D E F A Port Address 8 9 6 7 5 4 3 1 2 ---- P2DAT Aux. P2CR SC CWD Aux. CM P4DAT Aux. P4CR P5DAT Aux. P5CR ---- T12SUB Subport address 0 T2C 1 T2M1 2 T2M2 3 T2CM 4 T2CO1 5 T2CO2 6 ---- 7 ---- 8 T1C1 9 T1C2 A WDC B-F ASW STB SRB Aux. SIC1 SISC Aux. SIC2 ---- ---- RBR --- VMC VMST
Bidirectional Ports
Name
Write /Read
W W W W W W ---- ---- W W W
Timer 2 control register Timer 2 mode register 1 Timer 2 mode register 2 Timer 2 compare mode register Timer 2 compare register 1 Timer 2 compare register 2 (byte) Reserved Reserved Timer 1 control register 1 Timer 1 control register 2 Watchdog control register Reserved W 1111b Auxiliary / switch register W xxxx xxxxb Serial transmit buffer (byte) R xxxx xxxxb Serial receive buffer (byte) W 1111b Serial interface control register 1 W/RAAAAAA 1x11b Serial interface status / control register W 1111b Serial interface control register 2 Reserved Reserved W 0000b Rom bank switch register ---- Reserved W 1111b Voltage monitor control register R xx11b Voltage monitor status register
Reserved W/R 1111b Port 2 - data register / pin data W 1111b Port 2 - control register W 1x11b Port 3 - system configuration register R xxxxb Watchdog reset W/R 1111b Port 3 - clock management register W/R 1111b Port 4 - data register / pin data W 1111 1111b Port 4 - control register (byte) W/RAAAAAA 5 - data register / pin data 1111b Port W 1111 1111b Port 5 - control register (byte) Reserved W ---- Data to Timer 1/2 subport
Preliminary Information
0000b 1111b 1111b 0000b 1111b 1111 1111b ---- ---- 1111b x111b 1111b Reset Value
Port 4 4-bit wide bitwise-programmable bidirectional port also provides the I/O interface to Timer 2, SSI, voltage monitor input and external interrupt input.
Port 5 4-bit wide bitwise-programmable bidirectional port with optional static pull-ups and programmable interrupt logic.
Port 2 4-bit wide bitwise-programmable I/O port.
There are three different directional ports available:
Register Function
Rev. A1, 03-Apr-00
Module Type ASW M2 M3 M3 M3 M2 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M2 M3 M3 M2 M2 M2 See Page 14 14 19 46 47 45 46 45 27 27 28 34 35 36 37 37 37 19 21 21 18 26 17 24 24 23 23 8
T6020M
3.2.1 Bidirectional Port 2
This, and all other bidirectional ports include a bitwise programmable Control Register (P2CR), which enables the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin
I/O Bus Pull-up
condition when in output mode. This is a useful feature for self testing and for serial bus applications. Port 2 however, has an increased drive capability and an additional low resistance pull-up/-down transistor mask option.
V DD Static Pull-up
*
(Data out) I/O Bus D Q P2DATy S Master reset I/O Bus DSQ P2CRy (Direction)
*
* BP2y *
V DD
*
Pull-down
* Static
Pull-down
* Mask options Figure 19. Bidirectional Port 2
13388
Port 2 Data Register (P2DAT)
Primary register address: '2'hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAA AAAAA
P2DAT Reset value: 1111b * Bit 3 -> MSB, Bit 0 -> LSB
Bit 3 * P2DAT3
Bit 2 P2DAT2
Bit 1 P2DAT1
Bit 0 P2DAT0
Port 2 Control Register (P2CR)
Auxiliary register address: '2'hex P2CR Bit 3 P2CR3 Bit 2 P2CR2 Bit 1 P2CR1 Bit 0 P2CR0 Reset value: 1111b
Value: 1111b means all pins in input mode Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Function
BP20 in input mode BP20 in output mode BP21 in input mode BP21 in output mode BP22 in input mode BP22 in output mode BP23 in input mode BP23 in output mode
Rev. A1, 03-Apr-00
21 (54)
Preliminary Information
T6020M
3.2.2 Bidirectional Port 5
This, and all other bidirectional ports include a bitwise programmable Control Register (P5CR), which allows the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications. The port pins can also be used as external interrupt inputs (see figures 24 & 25). The interrupts (INT1 and INT6) can be masked or independently configured to trigger on either edge. The interrupt configuration and port direction is controlled by the Port 5 Control Register (P5CR). An additional low resistance pull-up/-down transistor mask option provides an internal bus pull-up for serial bus applications. The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of address '5'h and the Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is a byte-wide register and is configured by writing first the low nibble then the high nibble (see section 2.1 "Addressing peripherals").
V I/O Bus DD Pull-up V DD Static Pull-up
*
VDD (Data out) I/O Bus D Q P5DATy S Master reset IN enable
*
* BP5y *
V DD Static
*
* Pull-down
Pull-down
* Mask options Figure 20. Bidirectional Port 5
13359
INT1
Data in BP52
INT6
Data in BP51
Bidir. Port
IN_Enable
Bidir. Port
IN_Enable
I/O-bus
I/O-bus
Data in BP53
Data in BP50
Bidir. Port
IN_Enable Decoder Decoder Decoder Decoder
Bidir. Port
IN_Enable
P5CR: P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
13764
Figure 21. Port 5 external interrupts
22 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
Port 5 Data Register (P5DAT) Primary register address: '5'hex
AAAAAAAAAAAAA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA AAAAAAAAA A A AAAA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA A
Bit 3 Bit 2 Bit 1 Bit 0 P5DAT P5DAT3 P5DAT2 P5DAT1 P5DAT0 Reset value: 1111b Port 5 Control Register (P5CR) Byte Write Auxiliary register address: '5'hex Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 P5CR First write cycle P51M2 P53M2 P51M1 P53M1 P50M2 P52M2 P50M1 P52M1 Reset value: 1111b Reset value: 1111b Second write cycle P5xM2, P5xM1 - Port 5x Interrupt mode/direction code Auxiliary Address: '5'hex First Write Cycle Code Function 3210 x x 1 1 BP50 in input mode - interrupt disabled x x 0 1 BP50 in input mode - rising edge interrupt x x 1 0 BP50 in input mode - falling edge interrupt x x 0 0 BP50 in output mode - interrupt disabled 1 1 x x BP51 in input mode - interrupt disabled 0 1 x x BP51 in input mode - rising edge interrupt 1 0 x x BP51 in input mode - falling edge interrupt 0 0 x x BP51 in output mode - interrupt disabled Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Second Write Cycle Function BP52 in input mode - interrupt disabled BP52 in input mode - rising edge interrupt BP52 in input mode - falling edge interrupt BP52 in output mode - interrupt disabled BP53 in input mode - interrupt disabled BP53 in input mode - rising edge interrupt BP53 in input mode - falling edge interrupt BP53 in output mode - interrupt disabled Rev. A1, 03-Apr-00 23 (54)
Preliminary Information
T6020M
3.2.3 Bidirectional Port 4
and SD line have an additional mode to generate an SSI- interrupt. All four Port 4 pins can be individually switched by the P4CR-register . Figure 25 shows the internal interfaces to bidirectional Port 4. The bidirectional Port 4 is both a bitwise configurable I/O port and provides the external pins for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the same way as bidirectional Port 2 (see figure 22). Two additional multiplexes allow data and port direction control to be passed over to other internal modules (Timer 2, VM or SSI). The I/O-pins for SC
I/O Bus Intx PIn POut I/O Bus D S Master reset I/O Bus D (Direction) S Q Pull-down PDir Q PxDATy PxMRy
V
DD Static
*
VDD Pull-up
* Pull-up
*
BPxy *
VDD Static
*
* Pull-down
PxCRy
* Mask options Figure 22. Bidirectional Port 4
13360
Port 4 Data Register (P4DAT) Primary register address: '4'hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA
Bit 3 Bit 2 Bit 1 Bit 0 P4DAT P4DAT3 P4DAT2 P4DAT1 P4DAT0 Reset value: 1111b Port 4 Control Register (P4CR) Byte Write Auxiliary register address: '4'hex
AAAAAAAAA A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 P4CR First write cycle P41M2 P43M2 P41M1 P43M1 P40M2 P42M2 P40M1 P42M1 Reset value: 1111b Reset value: 1111b Second write cycle P4xM2, P4xM1 - Port 4x Interrupt mode/direction code 24 (54) Rev. A1, 03-Apr-00
Preliminary Information
T6020M
A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AA AA AA A A A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A
Code 3210 xx11 xx10 xx0x 11xx 10xx 01xx 00xx --- x x 0 0 BP40 enable alternate function (falling edge interrupt input for INT3) 1 1 x x BP41 in intput mode 1 0 x x BP41 in output mode 0 1 x x BP41 enable alternate function (VMI for voltage monitor input) 0 0 x x BP41 enable alternate function (T2I external clock input for Timer 2) BP42 in input mode BP42 in output mode BP42 enable alternate function (T2O for Timer 2) BP43 in input mode BP43 in output mode BP43 enable alternate function (SD for SSI) BP43 enable alternate function (falling edge interrupt input for INT3) ---
Auxiliary Address: '4'hex First Write Cycle Code Function 3210 x x 1 1 BP40 in input mode x x 1 0 BP40 in output mode x x 0 1 BP40 enable alternate function (SC for SSI)
Second Write Cycle Function
3.3
Universal Timer/Counter / Communication Module (UTCM)
put (T2I) and an output (T2O).
The Universal Timer/counter/ Communication Module (UTCM) consists of Timer 1, Timer 2 and a Synchronous Serial Interface (SSI). D Timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for Timer 2, the serial interface and the watchdog function. D Timer 2 is an 8/12-bit timer with an external clock inSYSCL SUBCL from clock module
D The SSI operates as two wire serial interface or as shift register for modulation. The modulator units work together with the timers and shift the data bits out of the shift register. There is a multitude of modes in which the timers and the serial interface can work together.
Timer 1
Watchdog MUX Interval / Prescaler NRST INT2
T1OUT MUX
Timer 2
4-bit Counter 2/1 Compare 2/1 Modu- lator 2 I/O bus T2O
T2I
POUT MUX DCG
Control 8-bit Counter 2/2 INT4 Compare 2/2
TOG2
SSI
Receive-Buffer 8-bit Shift-Register Transmit-Buffer
SCL
MUX
Control INT3
SC SD
13393
Figure 23. UTCM block diagram
Rev. A1, 03-Apr-00
25 (54)
Preliminary Information
T6020M
3.3.1 Timer 1
The Timer 1 is an interval timer which can be used to generate periodical interrupts and as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function. The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source for the Timer 1 interrupt. Because of other system requirements the Timer 1 output T1OUT is synchronized with SYSCL. Therefore in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) the output T1OUT is stopped (T1OUT=0). Nevertheless the Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the timer output can be programmed via the Timer 1 control register T1C1. This timer starts running automatically after any
SYSCL SUBCL
power-on reset ! If the watchdog function is not activated, the timer can be restarted by writing into the T1C1 register with T1RM=1. Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it overflows. The application software has to accomplish this by reading the CWD register. After power-on reset the watchdog must be activated by software in the $RESET initialization routine. There are two watchdog modes, in one mode the watchdog can be switched on and off by software, in the other mode the watchdog is active and locked. This mode can only be stopped by carrying out a system reset. The watchdog timer operation mode and the time interval for the watchdog reset can be programmed via the watchdog control register (WDC).
WDCL
MUX
CL1
Prescaler 14 bit
Watchdog 4 bit
NRST
INT2 T1CS T1MUX T1BP T1IM T1OUT
13766
Figure 24. Timer 1 module
T1C1 T1RM T1C2 T1C1 T1C0 3 Write of the T1C1 register
T1C2
T1BP T1IM
Decoder
MUX for interval timer
T1MUX
T1IM=0 INT2 T1IM=1 T1OUT
RES Q1 Q2 Q3 Q4 Q5 CL1 CL Q6
Q8 Q8
Q11 Q11
Q14 SUBCL Q14 Watchdog Divider / 8
Decoder
2 WDC WDL WDR WDT1 WDT0
MUX for watchdog timer WDCL
RES Read of the CWD register
13767
Divider RESET
RESET (NRST)
Watchdog mode control
Figure 25. Timer 1 and watchdog
26 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
Timer 1 Control Register 1 (T1C1)
Address: '7'hex - Subaddress: '8'hex
AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
T1C1 Reset value: 1111b * Bit 3 -> MSB, Bit 0 -> LSB T1RM T1C2 T1C1 T1C0 T1RM = 0, write access without Timer 1 restart T1RM = 1, write access with Timer 1 restart Note: if WDL = 0, Timer 1 restart is impossible Timer 1 Control bit 2 Timer 1 Control bit 1 Timer 1 Control bit 0 Timer 1 Restart Mode The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends on this divider and the timer 1 input clock source. The timer input can be supplied by the system clock or via the clock management.
T1C2 0 0 0 0 1 1 1 1 T1C1 0 0 1 1 0 0 1 1 T1C0 0 1 0 1 0 1 0 1 Divider 2 4 8 16 32 256 2048 16384
Bit 3 * T1RM
Bit 2 T1C2
Bit 1 T1C1
Bit 0 T1C0
If the clock management generates the SUBCL, the selected input clock from the RC oscillator or an external clock is divided by 16.
Time Interval with SYSCL = 2/1 MHz 1 ms / 2 ms 2 ms / 4 ms 4 ms / 8 ms 8 ms / 16 ms 16 ms / 32 ms 128 ms / 256 ms 1024 ms / 2048 ms 8192 ms / 16384 ms
Time Interval with SUBCL from Clock Management Tin 32 Tin 64 Tin 128 Tin 256 Tin 512 Tin 4096 Tin 32768 Tin 262144
Tin: input clock period = 1/Cin (see figure 14)
Timer 1 Control Register 2 (T1C2)
Address: '7'hex - Subaddress: '9'hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAA A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAA
T1C2 Reset value: x111b * Bit 3 -> MSB, Bit 0 -> LSB T1BP T1CS T1IM Timer 1 SUBCL ByPassed T1BP = 1, TIOUT = T1MUX T1BP = 0, T1OUT = SUBCL Timer 1 input Clock Select T1CS = 1, CL1 = SUBCL (see figure 28) T1CS = 0, CL1 = SYSCL (see figure 28) Timer 1 Interrupt Mask T1IM = 1, disables Timer 1 interrupt T1IM = 0, enables Timer 1 interrupt Rev. A1, 03-Apr-00 27 (54)
Bit 3 * ---
Bit 2 T1BP
Bit 1 T1CS
Bit 0 T1IM
Preliminary Information
T6020M
Watchdog Control Register (WDC)
Address: '7'hex - Subaddress: 'A'hex
A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
WDC Reset value: 1111b * Bit 3 -> MSB, Bit 0 -> LSB WDL WDR WDT1 WDT0 WatchDog Lock mode WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs. WatchDog Run and stop mode WDR = 1, the watchdog is stopped / disabled WDR = 0, the watchdog is active / enabled WatchDog Time 1 WatchDog Time 0 Both these bits control the time interval for the watchdog reset WDT0 Divider 0 1 0 1 512 2048 16384 131072 Delay Time to Reset with tin = 1/ (2 / 1 MHz) 0.256 ms / 0.512 ms 1.024 ms / 2.048 ms 8.2 ms / 16.4 ms 65.5 ms / 131 ms WDT1 0 0 1 1 tin: input clock period = 1/Cin (see figure 14)
Bit 3 * WDL
Bit 2 WDR
Bit 1 WDT1
Bit 0 WDT0
3.3.2
Timer 2
is possible to use Timer 2 with a higher clock speed than SYSCL. Furthermore with that input clock the Timer 2 operates in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in the POWERDOWN (CPU core -> sleep and OSC-Stop -> no). All other clock sources supplied no clock signal in SLEEP. The 4-bit counter stages of Timer 2 have an additional clock output (POUT). Its output has a modulator stage that allows the generation of pulses as well as the generation and modulation of carrier frequencies. The Timer 2 output can modulate with the shift register internal data output to generate Biphase- or Manchester-code. If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a special task. The shift register can only handle bitstream lengths divisible by 8. For other lengths, the 4-bit counter stage can be used to stop the modulator after the right bitcount is shifted out. If the timer is used for carrier frequency modulation, the 4-bit stage works together with an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty cycle. The 8-bit counter is used to en-
Features: 8/12 bit timer for D Interrupt, square-wave, pulse and duty cycle generation D Baud-rate generation for the internal shift register D Manchester and Biphase modulation together with the SSI D Carrier frequency generation together with the SSI and modulation
Timer 2 can be used as interval timer for interrupt generation, as signal generator or as baud-rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up counter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cascadable as 12-bit timer or as 8-bit timer with 4-bit prescaler. The timer can also be configured as 8-bit timer and separate 4-bit prescaler. The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer 1 output clock or the shift clock of the serial interface. The external input clock T2I is not synchronized with SYSCL. Therefore it
28 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
able and disable the modulator output for a programmable count of pulses. For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For programming the timer function, it has four mode and control registers. The comparator output of stage 2 is controlled by a special compare mode register (T2CM). This register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match event or the counter overflow. This architecture enables the timer function for various modes. Timer 2 compare data values The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. For 12-bit compare data value: m = x +1 0 x 4095 For 8-bit compare data value: n = y +1 0 y 255 For 4-bit compare data value: l = z +1 0 z 15
I/O-bus
P4CR
T2I
T2M1
T2M2
SYSCL T1OUT SCL
DCGO
CL2/1
4-bit Counter 2/1
RES OVF1 POUT
CL2/2
T2O
DCG
8-bit Counter 2/2
RES OVF2 TOG2
OUTPUT
M2 MOUT
T2C
Compare 2/1
CM1
Control
Compare 2/2
INT4
to Modulator 3
T2CO1
SSI POUT
T2CM
T2CO2
SO
Biphase-, Manchester- modulator
Timer 2 modulator output-stage
Control
I/O-bus SSI SSI
13394
Figure 26. Timer 2
Timer 2 Modes
Mode 1: 12-bit compare counter
POUT (CL2/1 /16) CL2/1
4-bit counter
RES
DCG
8-bit counter
RES
OVF2 TOG2
INT4
4-bit compare
CM1
8-bit compare
CM2 Timer 2 output mode and T2OTM-bit
4-bit register
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
13778
Figure 27. 12-bit compare counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match signal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. The compare action is programmable via the compare mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output (POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode. Rev. A1, 03-Apr-00 29 (54)
Preliminary Information
T6020M
Mode 2: 8-bit compare counter with 4-bit programmable prescaler
DCGO POUT CL2/1
4-bit counter
RES
DCG
8-bit counter
RES
OVF2 TOG2
INT4
4-bit compare
CM1
8-bit compare
CM2 Timer 2 output mode and T2OTM-bit
4-bit register
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
13778
Figure 28. 8-bit compare counter
The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output (CM1) supplies the clock output (POUT) with clocks.
Mode 3/4: 8-bit compare counter and 4-bit programmable prescaler
DCGO T2I SYSCL CL2/2 OVF2 TOG2 INT4
DCG
8-bit counter
RES CM2 Timer 2 output mode and T2OTM-bit P4CR P41M2, 1 T2D1, 0
8-bit compare
8-bit register
T2RM
T2OTM
T2IM
T2CTM
T1OUT SYSCL SCL
MUX
CL2/1
4-bit counter
RES CM1 POUT
4-bit compare
T2CS1, 0
4-bit register
13779
Figure 29. 4-/8-bit compare counter
In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input (T2I) which is selected via the P4CR register. The 4-bit prescaler is started via activating of mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for the 8-bit timer stage. The 4-bit stage can be used as prescaler for the SSI or to generate the stop signal for modulator 2.
Timer 2 Output Modes
The signal at the timer output is generated via modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes the DCG output is connected to T2O and switched on and off either by the toggle flipflop output or the serial data line of the
30 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
SSI. Modulator 2 also has 2 modes to output the content of the serial interface as Biphase or Manchester code. The modulator output stage can be configured by the output control bits in the T2M2 register. The modulator is started with the start of the shift register (SIR = 0) and
DCGO SO TOG2 RE Biphase/ Manchester modulator Toggle S1 RES/SET M2 S3 S2 T2O
stopped either by carrying out a shift register stop (SIR = 1) or compare match event of stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (SCL).
FE SSI CONTROL OMSK
M2 T2M2 T2OS2, 1, 0 T2TOP Figure 30. Timer 2 modulator output stage
13395
Timer 2 Output Signals
Timer 2 output mode 1: Toggle mode A: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Input Counter 2 T2R
0 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1
Counter 2 CMx INT4 T2O
13781
Figure 31. Interrupt timer / square wave generator - the output toggles with each edge compare match event
Rev. A1, 03-Apr-00
31 (54)
Preliminary Information
T6020M
Timer 2 output mode 1: Toggle mode B: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Input Counter 2 T2R Counter 2 CMx INT4 T2O
Toggle by start 0 0 0 1 2 3 4 5 6 7 4095/ 255 0 1 2 3 4 5 6
T2O
13782
Figure 32. Pulse generator - the timer output toggles with the timer start if the T2TS-bit is set
Timer 2 output mode 1: Toggle mode C: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Input Counter 2 T2R Counter 2 CMx OVF2 INT4 T2O Figure 33. Pulse generator - the timer toggles with timer overflow and compare match
0 0 0 1 2 3 4 5 6 7 4095/ 255 0 1 2 3 4 5 6
13783
Timer 2 output mode 2: Duty cycle burst generator 1:
the DCG output signal (DCGO) is given to the output, and gated by the output flip-flop (M2)
DCGO
1 2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
Counter 2 TOG2 M2 T2O
Counter = compare register (=2)
13784
Figure 34. Carrier frequency burst modulation with Timer 2 toggle flip-flop output
32 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
Timer 2 output mode 3: Duty cycle burst generator 2: the DCG output signal (DCGO) is given to the output, and gated by the SSI internal data output (SO)
DCGO
1201201201201201201201201201201201201201
Counter 2
Counter = compare register (=2)
TOG2 SO T2O
13785
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12 Bit 13
Figure 35. Carrier frequency burst modulation with the SSI data output
Timer 2 output mode 4: Biphase modulator:
Timer 2 modulates the SSI internal data output (SO) to Biphase code.
TOG2 SC
8-bit SR-Data
SO T2O
0 Bit 7 0 Data: 00110101
0 0 1
1 1
1
0 0 1
1
0 0
1 Bit 0 1
13786
Figure 36. Biphase modulation
Timer 2 output mode 5: Manchester modulator:
TOG2 SC
Timer 2 modulates the SSI internal data output (SO) to Manchester code
8-bit SR-Data
SO T2O
0 Bit 7 0 Bit 7 Data: 00110101 0
0 1
1 1
1 0
0 1
1 0
0 1
1 Bit 0 Bit 0
13787
Figure 37. Manchester modulation
Rev. A1, 03-Apr-00
33 (54)
Preliminary Information
T6020M
Timer 2 output mode 7: PWM mode: Pulse-width modulation output on Timer 2 output pin (T2O) In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period only the first compare match occurence is used to toggle the timer output flip-flop, until the overflow all further compare match are ignored. This avoids the stuation that changing the compare register causes the occurence of several compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit.
Input clock Counter 2/2 T2R
0 0 50 255 0 100 255 0 150 255 0 50 255 0 100
Counter 2/2 CM2 OVF2 INT4 T2O
T1 T load the next compare value T2CO2=150 load load
T2 T
T3 T
T1 T
T2
T 13788
Figure 38. PWM modulation
Timer 2 Registers
Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. All registers are indirectly addressed using extended addressing as described in section "Addressing peripherals". The alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.
Timer 2 Control Register (T2C)
Address: '7'hex - Subaddress: '0'hex
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T2C Reset value: 0000b T2CS1 T2CS0 Timer 2 Clock Select bit 1 Timer 2 Clock Select bit 0 T2CS1 0 0 1 1 T2CS0 0 1 0 1 Input Clock (CL 2/1) of Counter Stage 2/1 System clock (SYSCL) Output signal of Timer 1 (T1OUT) Internal shift clock of SSI (SCL) Reserved T2TS T2R Timer 2 Toggle with Start T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R Timer 2 Run T2R = 0, Timer 2 stop and reset T2R = 1, Timer 2 run 34 (54) Rev. A1, 03-Apr-00
Bit 3 T2CS1
Bit 2 T2CS0
Bit 1 T2TS
Bit 0 T2R
Preliminary Information
A AAAAAAAAAAA A A A AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AA AA AA A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A A AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
Timer 2 Mode Register 1 (T2M1)
T2MS1 T2MS0 T2D1 T2D0 T2M1 Timer 2 Mode Select bit 1 Timer 2 Mode Select bit 0 Timer 2 Duty cycle bit 1 Timer 2 Duty cycle bit 0 Mode 1 T2D1 1 1 0 0 4 3 2 T2MS1 1 Bit 3 T2D1 0 0 1 T2D0 1 0 1 0 T2MS0 Clock Output (POUT) 1 4-bit counter overflow (OVF1) Bit 2 T2D0 0 1 0 Function of Duty Cycle Generator (DCG) Bypassed (DCGO0) Duty cycle 1/1 (DCGO1) Duty cycle 1/2 (DCGO2) Duty cycle 1/3 (DCGO3) 4-bit compare output (CM1) 4-bit compare output (CM1) 4-bit compare output (CM1) Bit 1 T2MS1 Bit 0 T2MS0 Address: '7'hex - Subaddress: '1'hex Timer 2 Modes 12-bit compare counter, the DCG have to be bypassed in this mode 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler stop and resets Additional Divider Effect /1 /2 /3 /4
Rev. A1, 03-Apr-00 Duty Cycle Generator
DCGO3 DCGO2 DCGO1 DCGO0 DCGIN Figure 39. DCG output signals
13807
The duty cycle generator generates duty cycles from 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional programmable prescaler for Timer 2.
Preliminary Information
T6020M
Reset value: 1111b
35 (54)
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If one of these output modes is used the T2O alternate function of Port 4 must also be activated.
Timer 2 Mode Register 2 (T2M2)
T6020M
36 (54) T2OS2 T2OS1 T2OS0 T2TOP T2M2 Timer 2 Output Select bit 2 Timer 2 Output Select bit 1 Timer 2 Output Select bit 0 Timer 2 Toggle Output Preset This bit allows the programmer to preset the Timer 2 output T2O. T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0) T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1) Note: If T2R = 1, no output preset is possible Output Mode 1 7 8 6 5 4 3 2 Bit 3 T2TOP T2OS2 0 0 0 0 1 1 1 1 Bit 2 T2OS2 T2MS1 0 0 1 1 0 0 1 1 Bit 1 T2OS1 T2MS0 1 0 0 1 0 1 0 1 Bit 0 T2OS0
Preliminary Information
Toggle mode: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O Duty cycle burst generator 1: the DCG output signal (DCG0) is given to the output and gated by the output flip-flop (M2) Duty cycle burst generator 2: the DCG output signal (DCGO) is given to the output and gated by the SSI internal data output (SO) Biphase modulator: Timer 2 modulates the SSI internal data output (SO) to Biphase code Manchester modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code SSI output: T2O is used directly as SSI internal data output (SO) PWM mode: an 8/12-bit PWM mode Not allowed Clock Output (POUT) Address: '7'hex - Subaddress: '2'hex Reset value: 1111b Rev. A1, 03-Apr-00
T6020M
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2. The timer compares the contents of the compare register current counter value and if it matches it generates an output signal. Dependent on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next counter stage. In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit compare value. In all other modes, the two compare registers work independently as a 4- and 8-bit compare register. When assigned to the compare register a compare event will be supressed.
Timer 2 Compare Mode Register (T2CM)
Address: '7'hex - Subaddress: '3'hex
A A A A A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
T2CM Bit 3 T2OTM Bit 2 T2CTM Bit 1 T2RM Bit 0 T2IM Reset value: 0000b T2OTM T2CTM T2RM T2IM Timer 2 Overflow Toggle Mask bit T2OTM = 0, disable overflow toggle T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow can generate an interrupt except on the Timer 2 output mode 7. Timer 2 Compare Toggle Mask bit T2CTM = 0, disable compare toggle T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM-bit is set, only a match of the counter with the compare register can generate an interrupt. Timer 2 Reset Mask bit T2RM = 0, disable counter reset T2RM = 1, enable counter reset, a match of the counter with the compare register resets the counter Timer 2 Interrupt Mask bit T2IM = 0, disable Timer 2 interrupt T2IM = 1, enable Timer 2 interrupt Timer 2 Output Mode 1, 2, 3, 4, 5 and 6 1, 2, 3, 4, 5 and 6 7 T2OTM 0 1 x T2CTM x x 1 Timer 2 Interrupt Source Compare match (CM2) Overflow (OVF2) Compare match (CM2)
Timer 2 COmpare Register 1 (T2CO1)
Address: '7'hex - Subaddress: '4'hex
AAAAAAAAA AAAAAAAAA A A AAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA
T2CO1 Write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Timer 2 COmpare Register 2 (T2CO2) Byte Write
Address: '7'hex - Subaddress: '5'hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A AAAA A A AAAAAAAAA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA
T2CO2 First write cycle Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 Reset value: 1111b Reset value: 1111b Second write cycle Rev. A1, 03-Apr-00 37 (54)
Preliminary Information
T6020M
3.3.3 Synchronous Serial Interface (SSI)
2 and 3 wire NRZ 2 wire mode (I2C compatible) D With Timer 2: Biphase modulation Manchester modulation pulse-width demodulation Burst modulation register. The SSI can be configured in any one of the following ways: a) 2-wire external interface for bidirectional data communication with one data terminal and one shift clock. The SSI uses the Port BP43 as a bidirectional serial data line (SD) and BP40 as shift clock line (SC). b) 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The SSI uses BP40 as shift clock (SC), while the serial data input (SI) is applied to BP43 (configured in P4CR as input!). Serial output data (SO) in this case is passed through to BP42 (configured in P4CR to T2O) via the Timer 2 output stage (T2M2 configured in mode 6). c) Timer/SSI combined modes - the SSI used together with Timer 2 is capable of performing a variety of data modulation and functions (see Timer Section). The modulating data is converted by the SSI into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. SSI Features:
SSI Peripheral Configuration
The synchronous serial interface (SSI) can be used either for serial communication with external devices such as EEPROMs, shift registers, display drivers, other microcontrollers, or as a means for generating and capturing on-chip serial streams of data. External data communication takes place via the Port 4 (BP4) multi-functional port which can be software configured by writing the appropriate control word into the P4CR
I/O-bus
Timer 2 SIC1 SIC2 SISC SO Control SC SSI-Control Output /2
Shift_CL
SI SCI SC
INT3
TOG2 POUT T1OUT SYSCL
SO MSB 8-bit Shift Register LSB
SI SD
STB Transmit Buffer I/O-bus
SRB Receive Buffer
14221
Figure 40. Block diagram of the synchronous serial interface
General SSI Operation
The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers - the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for intermediate storage of data to be serially output. Both buffers are directly accessable by software. Transferring the parallel buffer data into and out of the shift register is controlled automatically by the SSI control, so that both single byte transfers or continuous bit streams can be supported.
The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or accept an external clock. The external shift clock is output on, or applied to the Port BP40. Selection of an external clock source is performed by the Serial Clock Direction control bit (SCD). In the combinational modes, the required clock is selected by the corresponding timer mode. The SSI can operate in three data transfer modes - synchronous 8-bit shift mode, I2C compatible 9-bit shift modes or 8-bit pseudo I2C protocol (without acknowledge-bit).
38 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
External SSI clocking is not supported in these modes. The SSI should thus generate and has full control over the shift clock so that it can always be regarded as an I2C Bus Master device. All directional control of the external data port used by the SSI is handled automatically and is dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This control bit defines whether the SSI is currently operating in Transmit (TX) mode or Receive (RX) mode. Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In the 9-bit I2C mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see I2C protocol). At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming data is automatically loaded into the receive buffer when the complete telegram has been received. Data can, if required thus be simultaneously received and transmitted. Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to `1' and data shifting resumed as soon as the application software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of the serial communication. The ACT bit remains high for the duration of the serial telegram or if I2C stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high.
8-bit Synchronous Mode
SC (rising edge) SC (falling edge) DATA SD/TO2 0 Bit 7 0 Bit 7 Data: 00110101 0 1 1 0 1 0 0 1 1 0 1 0 1 Bit 0 1 Bit 0
13823
Figure 41. 8-bit synchronous mode
In the 8-bit synchronous mode, the SSI can operate as either a 2 or 3 wire interface (see SSI peripheral configuration). The serial data (SD) is received or transmitted in NRZ format, synchronised to either the rising or falling edge of the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. When used together with one of the timer modulator or demodulator stages, the SSI must be set in the 8-bit synchronous mode 1. In RX mode, as soon as the SSI is activated (SIR= 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. This first telegram is automatically transferred into the receive buffer and the SRDY set to 0 indicating that the receive buffer contains valid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shifting in the following 8-bit telegram. If, during this time the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer and the SSI will continue clocking in the next telegram. Should, however, the first telegram not have been read (SRDY=1), then the SSI will stop, temporarily holding the second telegram in the shift register until a certain point of time when the controller is able to service the receive buffer. In this way no data is lost or overwritten. Deactivating the SSI (SIR=1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. This can be used for clocking in a data telegram of less than 8 bits in length. Care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivating the SSI (SIR=1) and terminating the reception. After termination, the shift register contents will overwrite the receive buffer.
Rev. A1, 03-Apr-00
39 (54)
Preliminary Information
T6020M
SC msb SD SIR SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) Write STB (tx data 1) Write STB (tx data 2) Write STB (tx data 3) tx data 1 lsb
0
msb tx data 2
lsb msb tx data 3
lsb
0
7654321
765432107654321
13824
Figure 42. Example of 8-bit synchronous transmit operation
SC msb lsb msb lsb 7654321076543210 rx data 1 SIR rx data 2 msb lsb 765432107654 rx data 3
SD
SRDY
ACT Interrupt (IFN = 0) Interrupt (IFN = 1) Read SRB (rx data 1) Read SRB (rx data 2) Read SRB (rx data 3)
13825
Figure 43. Example of 8-bit synchronous receive operation
9-bit Shift Mode
(I2C
compatible)
In the 9-bit shift mode, the SSI is able to handle the I2C protocol (described below). It always operates as an I2C master device, i.e., SC is always generated and output by the SSI. Both the I2C start and stop conditions are automatically generated whenever the SSI is activated or deactivated by the SIR-bit. In accordance with the I2C protocol, the output data is always changed in the clock low phase and shifted in on the high phase. Before activating the SSI (SIR=0) and commencing an I2C dialog, the appropriate data direction for the first word must be set using the SDD control bit. The state of this bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on the selected direction, either clocked into or out of the shift register. During the 9th clock period, the port direction is automatically switched over so that the 40 (54)
corresponding acknowledge bit can be shifted out or read in. In transmit mode, the acknowledge bit received from the slave device is captured in the SSI Status Register (TACK ) where it can be read by the controller. and in receive mode, the state of the acknowledge bit to be returned to the slave device is predetermined by the SSI Status Register (RACK ). Changing the directional mode (TX/RX) should not be performed during the transfer of an I2C telegram. One should wait until the end of the telegram which can be detected using the SSI interrupt (IFN =1) or by interrogating the ACT status. A 9-bit telegram, once started will always run to completion and will not be prematurely terminated by the SIR bit. So, if the SIR-bit is set to `1' in mit telegram, the SSI will complete the current transfer and terminate the dialog with an I2C stop condition. Rev. A1, 03-Apr-00
Preliminary Information
T6020M
Start SC msb SD lsb msb lsb Stop
76543210A tx data 1
76543210A tx data 2
SRDY
ACT Interrupt (IFN = 0) Interrupt (IFN = 1) SIR SDD Write STB (tx data 1) Write STB (tx data 2)
13826
Figure 44. Example of I2C transmit dialog
Start SC msb SD tx data 1 SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) SIR SDD Write STB (tx data 1) Read SRB (rx data 2) lsb msb rx data 2 lsb Stop
76543210A
76543210A
13827
Figure 45. Example of I2C receive dialog
8-bit Pseudo I2C Mode
In this mode, the SSI exhibits all the typical operational features except for the acknowledge-bit which is never expected or transmitted. I2 C
I2C Bus Protocol
The I2C protocol constitutes a simple 2-wire bidirectional communication highway via which devices can communicate control and data information. Although the I2C protocol can support multi-master bus
Rev. A1, 03-Apr-00
41 (54)
Preliminary Information
T6020M
configurations, the SSI, in I2C mode is intended for use purely as a master controller on a single master bus system. So all reference to multiple bus control and bus contention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Normally the communication channel is opened with a so-called start condition, which initializes all devices connected to the bus. This is then followed by a data telegram, transmitted by the master controller device. This telegram usually contains an 8-bit address code to activate a single slave device connected onto the I2C bus. Each slave receives this address and compares it with it's own unique address. The addressed slave device, if ready to receive data will respond by pulling the SD line low during the 9th clock pulse. This represents a so-called I2C acknowledge. The controller on detecting this affirmative acknowledge then opens a connection to the required slave. Data can then be passed back and forth by the master controller, each 8-bit telegram being acknowledged by the respective recipient. The communication is finally closed by the master device and the slave device put back into standby by applying a stop condition onto the bus. Data valid (4) The state of the data line represents valid data when, after START condition, the data line is stable for the duration of the HIGH period of the clock signal. Acknowledge All address and data words are serially transmitted to and from device in eight-bit words. The receiving device returns a zero on the data line during the ninth clock cycle to acknowledge word receipt.
C 1 n 8 9
D
Start
1st Bit
8th Bit
ACK
Stop
13833
(1) (2) SC
(4)
(4)
(3) (1)
Figure 47. I2C bus protocol 2
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit buffer empty or receive buffer full) at the end of SSI data telegram or on the falling edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed by the Interrupt FunctioN control bit (IFN). The SSI interrupt is usually used to synchronize the software control of the SSI and inform the controller of the present SSI status. The Port 4 interrupts can be used together with the SSI or, if the SSI itself is not required, as additional external interrupt sources. In either case this interrupt is capable of waking the controller out of sleep mode. To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Interrupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in P4CR register.
SD
Start condition
Data valid
Data change
Data valid
Stop condition
13832
Figure 46. I2C bus protocol 1
Bus not busy (1) Both data and clock lines remain HIGH.
Start data transfer (2) A HIGH to LOW transition of the SD line while the clock (SC) is HIGH defines a START condition.
Modulation
If the shift register is used together with Timer 2 for modulation purposes, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be used as conventional bidirectional ports. The modulation stage, if enabled, operates as soon as the SSI is activated (SIR=0) and ceases when deactivated (SIR=1).
Stop data transfer (3) A LOW to HIGH transition of the SD line while the clock (SC) is HIGH defines a STOP condition.
42 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
Due to the byte-orientated data control, the SSI when running normally generates serial bit streams which are submultiples of 8 bits. An SSI output masking (OMSK) function permits, however, the generation of bit streams of any length. The OMSK signal is derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programmable number of unrequired trailing data bits during the shifting out of the final data word in the bit stream. The number of non-masked data bits is defined by the value pre-programmed in the prescaler compare register. To use output masking, the modulator stop mode bit (MSM) must be set to '0' before programming the final data word into the SSI transmit buffer. This in turn, enables shift clocks to the prescaler when this final word is shifted out. On reaching the compare value, the prescaler triggers the OMSK signal and all following data bits are blanked.
Timer 2 CL2/1 SCL Compare 2/1 CM1
4-bit counter 2/1
OMSK Control
SO
SC
SSI-control Output
TOG2 POUT T1OUT SYSCL
SO /2 Shift_CL MSB 8-bit shift register SI LSB
13834
Figure 48. SSI output masking function
Rev. A1, 03-Apr-00
43 (54)
Preliminary Information
T6020M
Serial Interface Registers Serial Interface Control Register 1 (SIC1)
Auxiliary register address: '9'hex
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A A AAA A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A A AA
SIC1 SIR Reset value: 1111b SCD Serial Interface Reset SIR = 1, SSI inactive SIR = 0, SSI active Serial Clock Direction SCD = 1, SC line used as output SCD = 0, SC line used as input Note: This bit has to be set to '1' during the I2C mode Serial Clock source Select bit 1 Serial Clock source Select bit 0 SCS1 1 1 0 0 SCS1 SCS0 Note: with SCD = '0' the bits SCS1 and SCS0 are insignificant SCS0 1 0 1 0 Internal Clock for SSI SYSCL / 2 T1OUT / 2 POUT / 2 TOG2 / 2 * * * In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1). Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). In I2C modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition.
Bit 3 SIR
Bit 2 SCD
Bit 1 SCS1
Bit 0 SCS0
Serial Interface Control Register 2 (SIC2)
Auxiliary register address: 'A'hex SIC2 Bit 3 MSM Bit 2 SM1 Bit 1 SM0 Bit 0 SDD Reset value: 1111b
MSM
Modular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub-multiples of 8 bit. Serial Mode control bit 1 Mode Serial Mode control bit 0 1 2 3 4
SM1 SM0
SM1 SM0 SSI Mode 1 1 8-bit NRZ-Data changes with the rising edge of SC 1 0 8-bit NRZ-Data changes with the falling edge of SC 0 1 9-bit two-wire I2C compatible 0 0 8-bit two-wire pseudo I2C compatible (no acknowledge)
SDD
Serial Data Direction SDD = 1, transmit mode - SD line used as output (transmit data). SRDY is set by a transmit buffer write access. SDD = 0, receive mode - SD line used as input (receive data). SRDY is set by a receive buffer read access
Note: SDD controls port directional control and defines the reset function for the SRDY-flag
44 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
Serial Interface Status and Control Register (SISC)
Primary register address: 'A'hex
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SISC SISC write Reset value: 1111b read --- TACK ACT SRDY Reset value: xxxxb RACK TACK SIM IFN SRDY ACT Receive ACKnowledge status/control bit for I2C mode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram Transmit ACKnowledge status/control bit for I2C mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram Serial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. Interrupt FuNction IFN = 1, the serial interrupt is generated at the end of telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) Serial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive
Bit 3
Bit 2 RACK
Bit 1 SIM
Bit 0 IFN
Serial Transmit Buffer (STB) - Byte Write
Primary register address: '9'hex
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STB First write cycle Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 Reset value: xxxxb Reset value: xxxxb Second write cycle The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit. Rev. A1, 03-Apr-00 45 (54)
Preliminary Information
T6020M
Serial Receive Buffer (SRB) - Byte Read
Primary register address: '9'hex
AAAAAAAAA A AAAA A A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A
SRB First read cycle Bit 7 Bit 3 Bit 6 Bit 2 Bit 5 Bit 1 Bit 4 Bit 0 Reset value: xxxxb Reset value: xxxxb Second read cycle The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads content into the receive buffer when complete telegram has been received.
3.3.4
Combination Modes
The UTCM consists of one timer (Timer 2) and a serial interface. There is a multitude of modes in which the timers and serial interface can work together. The 8-bit wide serial interface operates as shift register for modulation. The modulator units work together with the timer and shift the data bits into or out of the shift register.
Combination Mode Timer 2 and SSI
I/O-bus
P4CR
T2I
T2M1
T2M2
DCGO SYSCL T1OUT reserved SCL CL2/1 4-bit Counter 2/1 RES OVF1 POUT CL2/2 T2O
DCG
8-bit Counter 2/2 RES OVF2 TOG2 INT4
OUTPUT
T2C
Compare 2/1
POUT
Timer 2 - control
CM1
Compare 2/2
MOUT Biphase-, Manchester- modulator
T2CO1
TOG2
T2CM
T2CO2
SO
Timer 2 modulator output-stage
Control
I/O-bus
SIC1
TOG2 POUT T1OUT SYSCL SCLI
SIC2
SISC
Control INT3 SO SC
SSI-control
Output
SO MSB
SCL
8-bit shift register
SI LSB
SD
Shift_CL
STB
Transmit buffer I/O-bus
SRB
Receive buffer 14222
Figure 49. Combination Timer 2 and SSI
46 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
Combination mode 1: Burst modulation SSI mode 1: 8-bit NRZ and internal data SO output to the Timer 2 modulator stage Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler and DCG Timer 2 output mode 3: Duty cycle burst generator
DCGO
1201201201201201201201201201201201201201
Counter 2
Counter = compare register (=2)
TOG2 SO T2O
13785
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12 Bit 13
Figure 50. Carrier frequency burst modulation with the SSI internal data output
Combination mode 2: Biphase modulation 1 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler Timer 2 output mode 4: The modulator 2 of Timer 2 modulates the SSI internal data output to Biphase code
TOG2 SC
8-bit SR-data
SO T2O
0 Bit 7 0 Data: 00110101
0 0 1
1 1
1
0 0 1
1
0 0
1 Bit 0 1
13786
Figure 51. Biphase modulation 1
Combination mode 3: Manchester modulation 1 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler Timer 2 output mode 5: The modulator 2 of Timer 2 modulates the SSI internal data output to Manchester code
TOG2 SC
8-bit SR-data
SO T2O
0 Bit 7 0 Bit 7 Data: 00110101 0
0 1
1 1
1 0
0 1
1 0
0 1
1 Bit 0 Bit 0
13787
Figure 52. Manchester modulation 1
Rev. A1, 03-Apr-00
47 (54)
Preliminary Information
T6020M
Combination mode 4: Manchester modulation 2 SSI mode 1: Timer 2 mode 3: Timer 2 output mode 5: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage 8-bit compare counter and 4-bit prescaler The modulator 2 of Timer 2 modulates the SSI data output to Manchester code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special mode to supply the prescaler with the shift-clock. The control output signal (OMSK) of the SSI is used as stop signal for the modulator. This is an example for a 12-bit Manchester telegram:
SCLI Buffer full SIR SO SC MSM Timer 2 Mode 3 SCL Counter 2/1 OMSK T2O
13837
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 4) 0 0 0 0 1 2 3
4
0
1
2
3
Figure 53. Manchester modulation 2
Combination mode 5: Biphase modulation 2 SSI mode 1: Timer 2 mode 3: Timer 2 output mode 4: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage 8-bit compare counter and 4-bit prescaler The modulator 2 of Timer 2 modulates the SSI data output to Biphase code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special mode to supply the prescaler via the shift-clock. The control output signal (OMSK) of the SSI is used as stop signal for the modulator. This is an example for a 13-bit Biphase telegram:
SCLI Buffer full SIR SO SC MSM Timer 2 Mode 3 SCL Counter 2/1 OMSK T2O
13838
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 5) 0 0 0 0 1 2 3
4
5
0
1
2
Figure 54. Biphase modulation
48 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
4
4.1
Electrical Characteristics
Absolute Maximum Ratings
Symbol VDD VIN tshort Tamb Tstg RthJA Tsld Value -0.3 to + 6.5 indefinite -40 to +85 -40 to +130 140 260 Unit V V s C C K/W C
Voltages are given relative to VSS
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AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A
VSS -0.3 VIN VDD +0.3
Parameters Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (SSO20) Soldering temperature (t 10 s)
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device
reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. VDD).
4.2
DC Operating Characteristics
Test Conditions / Pins Rext = 47 kW fSYSCL = fRCext / 2 fSYSCL = fRCext / 4 Rext = 47 kW fSYSCL = fRCext / 2 fSYSCL = fRCext / 4 fSYSCL = fRCext / 16 VDD = 6.5 V Symbol Min. Typ. Max. Unit
VDD = 5 V, VSS = 0 V, Tamb = -40 to 85C unless otherwise specified. Parameters Power supply Active current CPU active
IDD
330 170 40 35 30 0.5
370 190 45 40 35 0.8
mA mA mA mA mA mA
Power down current (CPU sleep, RC oscillator active)
IPD
Sleep current (CPU slepp, RC oscillator inactive)
ISleep
VDD = 5.5 V, VSS = 0 V, Tamb = -40 to 85C unless otherwise specified.
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IDD 370 190 45 40 35 410 210 50 45 40 mA mA mA mA mA Power down current (CPU sleep, RC oscillator active) IPD Rev. A1, 03-Apr-00 49 (54)
Parameters Active current CPU active
Test Conditions / Pins Rext = 47 kW fSYSCL = fRCext / 2 fSYSCL = fRCext / 4 Rext = 47 kW fSYSCL = fRCext / 2 fSYSCL = fRCext / 4 fSYSCL = fRCext / 16
Symbol
Min.
Typ.
Max.
Unit
Preliminary Information
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAA AAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAA A A A A AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAA AAAAAAA A A A AAAAAAA A A A AAAAAAAAAA AAAAAAAAAAAAA AA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AA A
Note: The Pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller VSS = 0 V, Tamb = -40 to 85C unless otherwise specified. All Bidirectional Ports Output HIGH current Parameters Input voltage LOW Input voltage HIGH Input LOW current (dyn. pull-up) Input HIGH current (dyn. pull-down) Input LOW current (stat. pull-up) Input LOW current (stat. pull-down) Output LOW current Test Conditions / Pins VDD = 3.5 to 6.5 V VDD = 3.5 to 6.5 V VDD = 3.5 V, VIL= VSS VDD = 6.5 V VDD = 3.5 V, VIH = VDD VDD = 6.5 V VDD = 3.5 V, VIL= VSS VDD = 6.5 V VDD = 3.5 V, VIH= VDD VDD = 6.5 V VOL = 0.2 VDD VDD = 3.5 V, VDD = 6.5 V VOH = 0.8 VDD VDD = 3.5 V, VDD = 6.5 V Symbol VIL VIH IIL IOH IOL IIH IIH IIL
0.8* VDD
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VSS = 0 V, Tamb = 25C unless otherwise specified.
T6020M
50 (54) Parameters Test Conditions / Pins Power-on reset threshold voltage POR threshold voltage BOT = 1 POR threshold voltage BOT = 0 POR hysteresis Voltage monitor threshold voltage VM high threshold voltage VDD > VM, VMS = 1 VM high threshold voltage VDD < VM, VMS = 0 VM low threshold voltage VDD > VM, VMS = 1 VM low threshold voltage VDD < VM, VMS = 0 External input voltage VMI VMI > VBG, VMS = 1 VMI VMI < VBG, VMS = 0 Symbol VMThh VMThh VMThl VMThl VVMI VVMI VPOR VPOR VPOR -15 -50 15 50 -120 -300 120 300 Min. VSS Min. 1.1 3.5 4.5 2.5 3.5 -3 -8 3 8 -30 -100 30 100 -250 -600 250 600 Typ. Typ. 1.25 1.25 -5 -16 5.0 5.0 4.0 4.0 3.0 4.0 50 5 15
Preliminary Information
Max. 0.2*VDD VDD -50 -200 50 200 -500 -1200 500 1200 Rev. A1, 03-Apr-00 Max. -8 -24 1.4 4.5 5.5 3.5 4.5 8 22 Unit V V A A A A A A A A Unit mA mA mA mA V V mV V V V V V V
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Supply voltage VDD = 2.5 to 6.5 V, VSS = 0 V, Tamb = 25C unless otherwise specified. VSS = 0 V Operation Cycle Time Parameters Test Conditions / Pins Timer 2 input timing Pin T2I Timer 2 input clock Timer 2 input LOW time Rise / fall time < 10 ns Timer 2 input HIGH time Rise / fall time < 10 ns Interrupt request input timing Int. request LOW time Rise / fall time < 10 ns Int. request HIGH time Rise / fall time < 10 ns External system clock EXSCL at OSC1 input ECM = EN Rise / fall time < 10 ns EXSCL at OSC1 input ECM = DI Rise / fall time < 10 ns Input HIGH time Rise / fall time < 10 ns Reset timing Power-on reset time VDD u VPOR RC oscillator 1 Frequency Stability VDD = 3.5 to 5.5 V Tamb = -40 to 85C Stabilization time VDD = 3.5 to 5.5 V RC oscillator 2 - external resistor Frequency Rext = 47 kW Stability VDD = 3.5 to 5.5 V Tamb = -40 to 85C Stabilization time VDD = 3.5 to 5.5 V External resistor Parameters System clock cycle Test Conditions / Pins VDD = 2.5 to 6.5 V Tamb = -40 to 85C Symbol Symbol tSYSCL fRcOut2 f/f fRcOut1 f/f fEXSCL fEXSCL fT2I tT2IL tT2IH tPOR tS Rext tIRL tIRH tIH tS Min. Min. 0.25 0.02 100 100 100 100 0.1 0.5 12 Typ. Typ. 1.6 1.5 47 4 Max. Max. 100 "10 "50 1 100 1 5 8 8
5
Rev. A1, 03-Apr-00
4.3
AC Characteristics
Preliminary Information
T6020M
51 (54) MHz % MHz % MHz MHz MHz ns ns Unit Unit ms ms ms s ns ns ms kW
T6020M
5 Package Information
5.7 5.3 6.75 6.50 4.5 4.3
Package SSO20
Dimensions in mm
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications 13007
1
10
52 (54)
Rev. A1, 03-Apr-00
Preliminary Information
T6020M
6 Ordering Information
Please select the option setting from the list below and insert ROM CRC. Output Input Output Input
Port 2
BP20 BP21 BP22 BP23 -
CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] -
Port 5
Pull-up Pull-down Pull-up static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static
BP50 -
CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] -
Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static
BP51 -
BP52 -
Port 4
BP53 -
BP40 BP41 BP42 BP43 -
ECM
External clock monitor
-
Enable Disable
Watchdog
Softlock Hardlock
Used oscillator
-
Ext. RC Ext. clock
File:____________. HEX
CRC: _____________ HEX
Approval
Date: ____-____-____
Signature: _______________
Rev. A1, 03-Apr-00
53 (54)
Preliminary Information
T6020M
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
1.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
54 (54)
Rev. A1, 03-Apr-00
Preliminary Information

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